Pipeline ADC's have been extensively used in electronic systems because they can offer both a high speed and a satisfying resolution. Increasing demand for performance improvement of such devices drive manufacturers to develop pipeline ADCs with higher speed, higher accuracy, lower power consumption and smaller die size and other improved properties. However, such effort is frustrated by some intrinsic limitations from the structural characteristics of conventional pipeline ADCs. For example, in order to ensure tolerable low levels of capacitor mismatch and KT/C noise, each stage of a conventional pipeline ADC requires at least two capacitors with a capacitance larger than a certain value, and thus adversely leads to increase in power consumption and die size.
FIG. 1 illustrates the architecture of a conventional pipeline ADC, in which an input analog signal is first obtained by a sample-and-hold (S/H) module 101 and subsequently propagates through a number of consecutive stages, for example, a first stage 1021, . . . , an i-th stage 102i, . . . , an n-th stage 102n and a last flash ADC stage 103, with each stage generating a corresponding number of digital bits, for example, K1 bits, . . . , Ki bits, . . . , Kn bits and Kn+1 bits. These bits are then fed to a shift register 104 as a digital signal, which is subsequently processed and output by a digital correction circuit 105. This pipeline ADC further includes a clock generation circuit 106 for generating clock signals and thereby switching the stages between different operation modes. In the case that the pipeline ADC of FIG. 1 is a 10-bit resolution one, implemented with the last stage as a 2-bit stage that contains a 2-bit parallel ADC and each of the other stages as a 1.5-bit stage that contains a 1.5-bit multiplying ADC (MADC), the 2-bit ADC owns no redundancy bit, while each 1.5-bit MADC can produce four possible binary code outputs, ‘00’, ‘01’, ‘10’ and ‘11’, in which the former three are effective and the last is redundant.
FIG. 2 is a schematic of a non-last stage of the pipeline ADC of FIG. 1. As illustrated, the i-th stage 102i includes an i-th sub-ADC 104 and a residue gain amplifier (i.e., a multiplying digital-to-analog converter (MDAC)) 105, and the MDAC 105 further includes a S/H 106, an i-th sub-DAC 107 and an operational amplifier (op-amp) 108. During operation, an input analog signal Vin is first sampled and held steady on the S/H 106, while the sub-ADC 104 converts the input analog signal Vin to a digital signal of Ki bits. Then the sub-DAC 107 converts the digital signal of Ki bits to a new analog signal, and the new analog signal is subtracted from the sampled input analog signal Vin to result in a residue signal. The residue signal of the subtraction is then amplified by the op-amp 108 to result in an output analog signal Vout, and the output analog signal Vout is fed to the next stage as an input analog signal thereof.
This process will be described in greater detail with reference to an example in which the MDAC 105 is exemplified as a 1.5-bit MDAC, for the sake of convenience in explanation. As shown in FIG. 3A, the stage of FIG. 2 includes two capacitors Cf and Cs, a sub-DAC 107a and an op-amp 108a. The sub-DAC 107a is realized by three switch-controlled reference voltage levels, Vref, 0 and −Vref, and produces an output voltage Vdac. The stage further includes: switches 109 and 110, both controlled by a first clock signal Φ1; and another switch 110 that is controlled by a second clock signal Φ2. A timing diagram of the two clock signals are shown in FIG. 3C. In the sampling phase, the switches 109 and 110 are closed to allow the input Vi to be stored on (i.e., sampled by) the capacitors Cf and Cs, while the switch 111 is open, leaving the op-amp 108a idle. At this time, the quantity of electric charge at the input terminal of the op-amp 108a is:Q1=−(Cs+Cf)Vi  (1)
On the other hand, when the 1.5-bit MDAC is in a holding phase, or referred to as “a residue amplification phase”, as shown in FIG. 3B, in which the associated stage gives an amplified residue as an output analog signal, the switches 109 and 110 are open, while the switch 111 is closed, electrically connecting the upper plate of the capacitor Cf to the output terminal of the op-amp 108a to activate the op-amp 108a. As a result, the output voltage Vdac of the sub-DAC 107a is applied on the upper plate of the capacitor Cs, and the quantity of electric charge at the input terminal of the op-amp 108a can be expressed as:Q2=(Vx−Vdac)Cs+(Vx−Vo)Cf  (2)
where Vo=A×(0−Vx), A represents the finite DC gain of the op-amp 108a, and Vx is the voltage at the input terminal of the op-amp 108a (i.e., the negative input terminal, since the positive input terminal is grounded, as illustrated).
According to the principle of charge conversation, from the equation Q1=Q2, the following formula can be obtained:
                              V          o                =                                            V              i                        ⁢                          A                                                β                  ⁢                                                                          ⁢                  A                                +                1                                              -                                    V              dac                        ⁢                                          C                s                                                              C                  s                                +                                  C                  f                                                      ⁢                          A                                                β                  ⁢                                                                          ⁢                  A                                +                1                                                                        (        3        )            
where, β is a feedback factor with the value of Cf/(Cf+Cs).
First-order approximating A/(βA+1) to 1/β×(1−1/βA) according to A/(βA+1)≈1/β×(1−1/βA) can modify formula (3) to:
                              V          o                =                                            V              i                        ⁢                                                            C                  s                                +                                  C                  f                                                            C                f                                      ⁢                          (                              1                -                                  1                                      β                    ⁢                                                                                  ⁢                    A                                                              )                                -                                    V              dac                        ⁢                                          C                s                                            C                f                                      ⁢                          (                              1                -                                  1                                      β                    ⁢                                                                                  ⁢                    A                                                              )                                                          (        4        )            
When assuming the amplification magnitude A of the op-amp 108a is an infinitely great number, formula (4) is further simplified to:
                              V          o                =                                            V              i                        ⁢                                                            C                  s                                +                                  C                  f                                                            C                f                                              -                                    V              dac                        ⁢                                          C                s                                            C                f                                                                        (        5        )            
During the operation of the conventional pipeline ADC comprised of a plurality of such stages that are interconnected together, when a certain stage is in the holding phase as shown in FIG. 3B, the adjacent, subsequent stage will operate in the sampling phase as shown in FIG. 3A. Accordingly, an output analog signal V0 of the op-amp 108a of the upstream stage will be taken as an input signal Vi for the downstream stage and is sampled by the capacitors Cf and Cs thereof. As a result, as implied in formula (5), the capacitors Cf and Cs of each stage of the conventional pipeline ADC must assume a capacitance that is larger than a certain value. This may lead to increase in the power consumption and die size.